1. Field of the Invention
This invention relates to the field of master-slave flip-flop circuits. More particularly, this invention relates to master-slave retention flip-flop circuits which operate in a normal mode controlled by a clock signal and in a retention mode in which the slave state is maintained and less power consumed.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings illustrates one known master-slave retention flip-flop circuit. In this circuit the received clock signal is combined in an AND gate 2 with a retention signal to produce the local clock signals cn and c which are used to control the master/slave retention flip-flop circuit. When the retention signal input to the AND gate 2 goes low, the local clock signals supplied to the flip-flop are held static and so the data output by the slave stage of the flip-flop remains constant.
A problem with this circuit is that, if the clock signal input to the AND gate 2 is high and the retention signal goes from low to high, then there will be a transition in the local clock signals cn and c which control the flip-flop circuitry. This is functionally incorrect as the output of the flip-flop circuit should not change when the clock signal input to the AND gate 2 is steady.
FIG. 2 of the accompanying drawings illustrates another known design of a master-slave retention flip-flop circuit. The operation of this circuit is such that, if the clock signal CK is high, then the retained data within the retention latch (dark inverters) will pass to the output Q and the output of the master stage will be blocked by the tri-state inverter in the master latch.
A problem with this circuit is, if the clock signal CK is low and a local power up occurs while in the retention mode, then the value driven to the output Q is not well defined.
An object of the present invention is to provide a clock independent master-slave flip-flop circuit that has correct functional behaviour for a flip-flop and a well defined output independent of the clock signal level.